IC Design Goes Green

The illustration shows the levels of abstraction involved in digital IC design. Catapult C Synthesis high level synthesis software takes a high-level, untimed C/C++ description and synthesizes it into a verified hardware implementation for either ASIC or FPGA designs.
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In today's designs, application-specific integrated circuits (ASIC) and field-programmable gate arrays (FPGA) must dissipate as little power as possible. Low dissipation ICs comply with government efficiency regulations, fulfill customer demand for green products, and meet the need for longer battery life in handheld and mobile devices. ICs that dissipate too much power can also force designers to use a more expensive package.

A number of ideas have sprung up to help electronic-device makers cut power at the IC level. However, these approaches require significant design expertise — which is scarce. It is also problematic to verify these techniques using the manual approach designers rely on out of habit and necessity.

However, high level synthesis (HLS) software is addressing these issues by automating power optimization while providing a quick path from specifications written in C++ to hardware implementation. HLS software gives users a more abstract and therefore easier, faster approach than that of working directly at the register transfer level (RTL).

The register transfer level defines circuit behavior in terms of the flow of signals between hardware registers and the logical operations performed on those signals. Because traditional RTL coding is done manually, designers can create only one version of a design, which may not be optimal in terms of power, area, and performance. High level synthesis software, on the other hand, automates RTL code generation. This lets designers easily create multiple versions of the same design that are functionally identical, but provide a range of options for balancing power, circuit area, and performance — the so-called “primary colors” of electronic design.

Basics of IC Design

The Catapult C Synthesis GUI lets designers use the same C code (left-hand side), to quickly explore different hardware implementations and compare circuit area, timing, and power using tables, XY plots, and other graphical representations.
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Before looking more closely at HLS tools, it is first helpful to understand the role of “abstraction” in IC design. The higher the level of abstraction, the easier it is for engineers to design, verify, and modify circuit function. As a design moves from original concept to the final IC, the representation becomes more detailed, reflecting the additional decisions and information added to the model description. When automated, this process of transforming the design description to a lower level of abstraction is called “synthesis.”

HLS software such as Mentor Graphic's Catapult C Synthesis tool translates the original design specification, generally written in C++, to a hardware-description language like Verilog or VHDL. The input model for HLS is more abstract than for the RTL in the sense that the source code is a functional description only; there are no timing or concurrence definitions. The HLS model is also technology-neutral; it can be used with any chip technology.