IC Design Goes Green

Jan 1, 2010 12:00 PM,

Thomas Bollaert Mentor Graphics Corp. Wilsonville, Ore.

High level synthesis software provides an efficient path from algorithm concept to silicon, while slashing IC power consumption.

Another power-reduction technique is called clock gating. Here, designers place an “enabler” gate between a particular register and the clock that drives it. This arrangement lets the register be turned on or off independently. This is like turning the lights on only when you are in a room and turning them off when you leave. From a lower-power point-of-view, the best way to do this is to gate all registers individually.

Currently, most designers use a “global enable” command to fully suspend or enable the whole design because of the incredible amount of work it takes to implement clock gating at the register level. To continue the analogy, this is like either having every light in your house on or every light off. HLS software can perform multi-level clock gating, which identifies all clock-gating candidates in a design. In an automated fashion, Catapult analyzes every register in turn, figures out when and how they can be suspended, and builds the proper control logic to drive the enablers. Because it builds all possible clock-gating candidates, whenever a register can be clock gated, the software produces the structure to gate it. This approach optimizes designs' power consumption far better than designers can do by hand. Users see power reductions of anywhere between 40% to 90%.

Frequency and voltage scaling

Dynamic frequency scaling is on the leading edge of low-power design optimization. Like multi-level clock gating, it is a subtle yet powerful way to improve the on-off approach used in global clock gating. The idea is to drive the design with a slower clock than usual for non-critical tasks.

In a digital IC design, the switching power, or dynamic power is measured by

C × V2 × f

where C is capacitance, V is voltage, and f is frequency. Thus, slowing the clock and scaling down the frequency linearly reduces the power consumed. The IC still takes the same number of cycles to perform a task, but each cycle takes longer due to the slower clock. This approach dissipates less energy. Dynamic voltage scaling works much the same way but through voltage management. Power savings in this case follow a geometric progression.

High level synthesis tools are useful here because they provide power-management algorithms to determine when to slow down parts of a design and the high-level knowledge to build the blocks correctly. For example, Catapult C tells the power-management units what the blocks are doing and then lets the designer make the correct decision about how to drive them.

A Balancing Act

Just as there are many ways to skin a cat, a given functionality can be implemented at the RTL in many different ways, with each having a different balance of performance, power, and area. However, RTL designers rarely, if ever, have the time to try out different combinations of these variables. They write one implementation that works, and then they optimize it. Ironically, RTL synthesis tools give an accurate measurement of these three attributes, yet there is not enough time to create and assess more than one RTL netlist. So any optimizations to the RTL remain within the bounds of that initial attempt, even if it is obvious that a different netlist would do better.

In contrast, high level synthesis tools automatically create multiple RTL netlists so designers can analyze a variety of scenarios. HLS can generate dozens of implementations in literally minutes, and each of these solutions has an area, performance, and power value.

A closer look at digital IC design

This kind of design entails:

Working on the electronic system level (ESL), where a designer writes the original specification which defines what he wants the chip to do based on criteria for a specific product. To write the spec, engineers can use a variety of languages and tools such as C/C++ or Simulink and Matlab.
Next comes converting the specification into a register transfer level (RTL) description. This describes the behavior of the digital circuits on the chip and the connections to I/Os.
Lastly, designers combine the RTL description with available logic gates to create a chip design. This involves selecting the proper gates, defining their locations, and wiring them together.